Analysis of Dynamic Latched Comparator with Reduced Delay and Energy for High Speed ADCs

Bhuvaneswari N¹

¹Assistant Professor, Department of ECE, Vidyaa Vikas College of Engineering and Technology, Tiruchengode, India

Abstract

Design and analysis of Low-power, area efficient and high speed analogue-to-digital converters are pushing toward the use of dynamic comparators, which is used to maximize speed and power efficiency. In the existing design, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the trade-offs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed; where the circuit of a conventional double tail comparator is modified for low-power and fast operation where supply voltages down to 1.2V. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. This paper presents a CMOS comparator that reduces the overall propagation delay and hence provides higher speed. The design is simulated in 0.18μm CMOS Technology using Tanner EDA Tools. CMOS Comparator shows that the overall propagation delay of the comparator, TPD, is 1.4872e-9 seconds, with a 1.0 V supply voltage.

Keywords

• Analog to Digital Converter (ADC), Ultra Deep Sub Micrometer (UDSM), Double Tail Comparator, CMOS

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Cite this Article as Follows

Bhuvaneswari N. Analysis of Dynamic Latched Comparator with Reduced Delay and Energy for High Speed ADCs. International Conference on Advances & Challenges in Interdisciplinary Engineering and Management (2017): 08. Print.