Power Analysis of Embedded Low Latency Network on Chip

Hemasundari H¹, R Anandha Praba²

¹PG student, M.E. Applied Electronics, ²Assistant professor, ECE Department, Meenakshi College of Engineering, Chennai, India

Abstract

A Network-on-chip (NOC) is a new paradigm in complex system-on-chip (SOC) designs that provide efficient on chip communication networks. The data is routed through the networks in terms of packets. The routing of data is mainly done by routers. So the architecture of router must be an efficient one with a lower latency and higher throughput. In this project we designed, implemented and analyzed crossbar router architectures for a network on chip communication in a FPGA. The routers have five ports, four ports connected to other ports in four different directions and the fifth port connected to the processing element through a network interface. Our Proposed architecture contains 4x4 crossbar switch, switch allocator, path and channel request, data ram and 4 i/o ports. The datas ere sent through the routers in order to prevent congestion. The swich allocator and VC allocator are used to allocate the datas in priority order. The switch allocator will allocate the datas according to the path and channel request. The XY algorithm with a scheduler is used in this project for proper destination of the datas.

Keywords

• NOC, FPGA, switch allocator, VC alloctor, ports

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Cite this Article as Follows

Hemasundari H, R Anandha Praba. "Power Analysis of Embedded Low Latency Network on Chip" International Conference on Computer Applications (2016): 46-49. Print.