A Novel Voltage-Mode Lut Using Clock Boosting Technique in Standard CMOS

Sathyavathi N S¹

¹Department of VLSI Design, Adhiparasakthi Engineering College, Melmaruvathur, TN, India

Abstract

In a VLSI circuit, interconnection plays the dominant role in every part of the circuit nearly 70 percent of the area depends on interconnection, 20 percent on insulation, and remaining 10 percent to devices. The binary logic is limited due to interconnect which occupies a large area on a VLSI chip. In this work, the designs of quaternary-valued logic circuits have been explored over multi-valued logic due to the following reasoning. An approach to mitigate the impact of interconnections is to use multiple-valued logic (MVL) , hence, more information can be carried in each wire, reducing the routing network. Therefore, a single wire carrying a signal with N logic levels can replace [log2N] wires carrying binary signals. Therefore, this results in increasing the maximum operation frequency and also reducing the power consumption. Our new clock boosting method overcomes convectional techniques with simple and efficient CMOS structures.

Keywords

• Multiple-value Logic, Quaternary logics, Look- up tables, FPGAs, Standard CMOS Technology

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Cite this Article as Follows

Sathyavathi N S. A Novel Voltage-Mode Lut Using Clock Boosting Technique in Standard CMOS. International Conference on Innovative trends in Electronics Communication and Applications 2014. Vol. 1. Chennai: Association of Scientists, Developers and Faculties, 2014. 420-426. Print.