ICSSCCET 2015

International Conference on Systems, Science, Control, Communication, Engineering and Technology 2015

 


ICSSCCET 2015 Kokula Krishna Hari K
Publication Meta Value
Short Title ICSSCCET 2015
Publisher ASDF, India
ISBN 13 978-81-929866-1-6
ISBN 10 81-929866-1-6
Language English
Type Hard Bound - Printed Book
Copyrights ICSSCCET Organizers / DCRC, London, UK
Editor-in-Chief Ramachandran T
Conference Dates 10 - 11, August 2015
Venue Country Karpagam Institute of Technology, Coimbatore, India
Submitted Papers 410
Acceptance Rate 4.11%
Website www.icssccet.org

Paper 033


A Level-up Shifter using MTCMOS Technique for Power Minimization

A Level-up Shifter using MTCMOS Technique for Power Minimization

T Arthi1, N Preetha2

1, 2 Assistant Professor, Department of ECE.
Karpagam Institute of Technology, Coimbatore.

Abstract

Level shifter is an interfacing circuit which can interface low core voltage to high input-output voltage. It allows communication between different modules without adding up any extra supply pin. The main objective of the work is to minimize power dissipation in shifter circuit, which is due to different supply voltages in the circuit. The proposed method uses MTCMOS technique, which is one of the low power design technique to achieve power minimization. The new circuit uses the multi-threshold CMOS technique to provide a wide voltage conversion . The proposed design is implemented in CADENCE Virtuoso 180-nm CMOS technology. The new LS reaches a propagation delay value of 17 ns, a static power dissipation of only 115.3 pW, for a 1-MHz input pulse.

Author's Profile

T Arthi : Profile

N Preetha : Profile

Cite this Article as Follows

T Arthi, N Preetha."A Level-up Shifter using MTCMOS Technique for Power Minimization." International Conference on Systems, Science, Control, Communication, Engineering and Technology (2015): 155-158. Print.