ICSSCCET 2015

International Conference on Systems, Science, Control, Communication, Engineering and Technology 2015

 


ICSSCCET 2015 Kokula Krishna Hari K
Publication Meta Value
Short Title ICSSCCET 2015
Publisher ASDF, India
ISBN 13 978-81-929866-1-6
ISBN 10 81-929866-1-6
Language English
Type Hard Bound - Printed Book
Copyrights ICSSCCET Organizers / DCRC, London, UK
Editor-in-Chief Ramachandran T
Conference Dates 10 - 11, August 2015
Venue Country Karpagam Institute of Technology, Coimbatore, India
Submitted Papers 410
Acceptance Rate 4.11%
Website www.icssccet.org

Paper 024


Efficient Implementation of Fast FCS Architecture using Viterbi Coders

Efficient Implementation of Fast FCS Architecture using Viterbi Coders

R R Thirrunavukkarasu1, R Satheeshkumar2

1, 2 Assistant Professor, Department of ECE
1Karpagam Institute of Technology
2KSR College of Technology, Coimbatore.

Abstract

Viterbi algorithm is widely used as a decoding technique for convolutional codes as well as a bit detection method in storage devices. The design space for VLSI implementation of Viterbi decoders is huge, involving choices of throughput, latency, area, and power. This Paper propose Fast ACS architecture to reduce the area and power of the ACS unit in viterbi decoder. With the proposed structure it is possible to reduce the area and power of the ACS unit by 30% to 40% compare to conventional ACS architecture. The results are based on real designs for which actual synthesis and layouts are obtained using synopsys.

Author's Profile

R R Thirrunavukkarasu : Profile

R Satheeshkumar : Profile

Cite this Article as Follows

R R Thirrunavukkarasu, R Satheeshkumar."Efficient Implementation of Fast FCS Architecture using Viterbi Coders." International Conference on Systems, Science, Control, Communication, Engineering and Technology (2015): 120-123. Print.