ICIEMS 2015

International Conference on Information Engineering, Management and Security 2015

 


ICIEMS 2015 Kokula Krishna Hari K
Publication Meta Value
Short Title ICIEMS 2015
Publisher ASDF, India
ISBN 13 978-81-929742-7-9
ISBN 10 81-929742-7-8
Language English
Type Hard Bound - Printed Book
Copyrights ICIEMS Organizers / DCRC, London, UK
Editor-in-Chief Kokula Krishna Hari K
Conference Dates 13 - 14, August 2015
Venue Country IITM-RP, Chennai, India
Submitted Papers 410
Acceptance Rate 4.11%
Website www.iciems.in

Paper 033


Optimization of the critical loop in Renormalization CABAC decoder

Optimization of the critical loop in Renormalization CABAC decoder

Karthikeyan C1, Rangachar2

1Assistant Professor, ECE Department, MNM Jain Engg.College, Chennai, Research scholar, Hindustan University, Chennai-603103, 2Senior Professor, Dean for school of electrical science, Hindustan University, Chennai, INDIA

Abstract

Context-based adaptive binary arithmetic coding (CABAC) is needed in the present days for high speed H.264/AVC decoder. The high speed is achieved by decoding one symbol per clock cycle using parallelism and pipelining techniques. In this paper we present an innovative hardware implementation of the renormalization which is a part of CABAC binary arithmetic decoder. The renormalization of range and value is specified as a sequential loop process that shifts only one bit per cycle until the range and value are renormalized. To speed up this process, a special hardware technique is used. The hardware will take one clock cycle to shift n bit data. The proposed hardware is coded using HDL language and synthesized using Xilinx CAD tool.

Author's Profile

Karthikeyan C : Profile

Rangachar : Profile

Cite this Article as Follows

Karthikeyan C, Rangachar. "Optimization of the critical loop in Renormalization CABAC decoder." International Conference on Information Engineering, Management and Security (2015): 199-203. Print.